1. Field of the Invention
The present invention relates generally to a method for forming a stacked gate, and more specifically to a gate forming process relating to a silicon layer on a barrier layer.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First, manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as multi-gate MOSFET devices. With the trend towards scaling down the size of semiconductor devices, however, conventional poly-silicon gates face problems such as inferior performance due to boron penetration and unavoidable depletion effect. This increases the equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals that are suitable for use as a high-K gate dielectric layer are used to replace the conventional poly-silicon gate as the control electrode.